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http://www.ubuntugeek.com

The goal of the MyHDL project is to empower hardware designers with the elegance and simplicity of the Python language.
MyHDL is a free, open-source package for using Python as a hardware description and verification language. Python is a very high level language, and hardware designers can use its full power to model and simulate their designs. Moreover, MyHDL can convert a design to Verilog or VHDL. This provides a path into a traditional design flow.

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Created by FamilyGuy 9 years 2 weeks ago
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